nvc
NVC is a VHDL compiler and simulator
NVC is a VHDL compiler and simulator. NVC supports almost all of VHDL-2008 with the exception of PSL, and it has been successfully used to simulate several real-world designs. Experimental support for VHDL-2019 is under development. NVC has a particular emphasis on simulation performance and uses LLVM to compile VHDL to native machine code. NVC is not a synthesizer. That is, it does not output something that could be used to program an FPGA or ASIC. It implements only the simulation behaviour of the language as described by the IEEE 1076 standard. NVC supports popular verification frameworks including OSVVM, UVVM, and VUnit.
homepage ↗homepage ↗ github: nickg/nvc sourcehut: ~nickg/nvc
Available in
| Overlay | Newest | Ebuilds | Last activity | |
|---|---|---|---|---|
| gentoo gitweb ↗ | 1.21.1-r1 | 1 | 16 h | details › |
Versions & arches
Use flags of 1.21.1-r1
- llvm Build LLVM code generator
- test Enable dependencies and/or preparations necessary to run tests (usually controlled by FEATURES=test but can be toggled independently)
3 expansion flags (python targets, ABIs, cpu flags…)
- +llvm_slot_22
- llvm_slot_20
- llvm_slot_21