iverilog
A Verilog simulation and synthesis tool
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2001.
homepage ↗homepage ↗ github: steveicarus/iverilog
Available in
| Overlay | Newest | Ebuilds | Last activity | |
|---|---|---|---|---|
| gentoo gitweb ↗ | 13.0 | 3 | 17 h | details › |
| vowstar GitHub ↗ | 13.0 | 3 | 28 h | details › |
Versions & arches
| Version | Overlay | amd64 | arm64 | x86 | ppc64 | riscv | arm | ppc | Committed | |
|---|---|---|---|---|---|---|---|---|---|---|
| 9999 LIVE | gentoo | follows upstream — no keywords | — | view · download · history ↗ | ||||||
| 9999 LIVE ≈ | vowstar | follows upstream — no keywords | 4 mo | view · download · history ↗ | ||||||
| 13.0 | gentoo | amd64 stable | arm64 testing | x86 testing | ppc64 testing | riscv testing | arm testing | ppc testing | — | view · download · history ↗ |
| 13.0 ≈ | vowstar | amd64 untested | arm64 untested | x86 untested | ppc64 untested | riscv untested | arm untested | ppc untested | 4 mo | view · download · history ↗ |
| 12.0-r1 | gentoo | amd64 stable | arm64 testing | x86 testing | ppc64 testing | riscv testing | arm testing | ppc testing | — | view · download · history ↗ |
| 12.0-r1 ≈ | vowstar | amd64 untested | arm64 untested | x86 untested | ppc64 untested | riscv untested | arm untested | ppc untested | 4 mo | view · download · history ↗ |